Samsung Electronics today announced a wafer level packaging (WLP) technology for 512Mbit DDR2 chips that can enhance electrical properties and reduces physical space of the chips. The new package technology has two patterned inter-layer dielectrics (ILD), with insulating characteristics, and a metal layer replaces the conventional package substrate. The package enhances electrical properties though shorter circuit-routing, reduces package size to die level and package process time, and improves productivity – especially for larger wafer sizes – with higher throughput and lower cost.
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